indus t rial po wer c o ntrol eic e dr iv er ? co m pac t hig h voltage gate driver ic final dat a s heet , 01.06.2016 final 2e dl fa mi ly 600 v half bridge gate drive ic 2EDL23I06PJ 2edl23n06pj eicedriver? compact
edition 01.06.2016 published by infineon technologies ag 81726 munich, germany ? 2016 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respe ct to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitati on, warranties of non - infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon techn ologies components may be used in life - support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life - support device or system or to a ffect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that th e health of the user or other persons may be endangered.
eicedriver? compact 2edl family final datasheet 3 , 01.06.2016 revision history page or item su bjects (major changes since previous revision) , 15.05.2014 all change term vcc in vdd , 01.06.2016 u pdate maximum ta from 95 o c to 105 o c in table 5 trademarks of infineon technologies ag aurix?, bluemoon?, c166?, canpak?, cipos?, cipurse?, comneon?, econopack?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobridge?, econodual?, econopim?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my - d?, novalithic?, omnitune?, optimos?, origa?, primarion?, primepack?, primestack?, pro - sil?, profet?, rasic?, reversave?, satric?, sieget?, sindrion?, sipmos?, smarti?, smartlewis?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?, x - gold?, x - pmu?, xmm?, xposys?. other trademarks advance design system? (ads) of agilent technologies, amba?, arm?, multi - ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat - iq? of dect foru m. colossus?, firstgps? of trimble navigation ltd. emv? of emvco, llc (visa holdings inc.). epcos? of epcos ag. flexgo? of microsoft corporation. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission elect rotechnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mif are? of nxp. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwave? openwave systems inc. red ha t? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektronix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments incorporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex li mited . last trademarks update 2010 - 10 - 26
eicedriver? compact 2edl family final datasheet 4 , 01.06.2016 table of contents 1 overview ................................ ................................ ................................ ................................ ............. 7 2 blockdiagram ................................ ................................ ................................ ................................ ...... 9 3 pin configur ation, description, and functionality ................................ ................................ ......... 10 3.1 pin configuration and description ................................ ................................ ................................ ...... 10 3.2 low side and high side control pins (lin, hin) ................................ ................................ ............... 10 3.2.1 input voltage range ................................ ................................ ................................ ............................ 10 3.2.2 switching levels ................................ ................................ ................................ ................................ .. 10 3.2.3 input filter time ................................ ................................ ................................ ................................ .... 11 3.3 vdd, gnd and pgnd (low side supply) ................................ ................................ ......................... 11 3.4 vb and vs (high side supplies) ................................ ................................ ................................ ........ 11 3.5 lo and ho (low and high side outputs) ................................ ................................ .......................... 11 3.6 undervoltage lockout (uvlo) ................................ ................................ ................................ ............ 12 3.7 bootstrap diode ................................ ................................ ................................ ................................ .. 12 3.8 dead time and interlock function ................................ ................................ ................................ ......... 12 3.9 en - /flt (fault indication and enable function) ................................ ................................ ................... 12 3.10 power ground / over current protection ................................ ................................ .............................. 13 4 electrical parameters ................................ ................................ ................................ ....................... 14 4.1 absolute maximum ratings ................................ ................................ ................................ ............... 14 4.2 required operation conditions ................................ ................................ ................................ ........... 15 4.3 operating range ................................ ................................ ................................ ................................ 15 4.4 static logic function table ................................ ................................ ................................ ................... 16 4.5 static parameters ................................ ................................ ................................ ............................... 16 4.6 dynamic parameters ................................ ................................ ................................ .......................... 18 5 timi ng diagrams ................................ ................................ ................................ ............................... 19 6 package ................................ ................................ ................................ ................................ ............. 22 6.1 pg - dso - 14 ................................ ................................ ................................ ................................ ........ 22
eicedriver? compact 2edl family final datasheet 5 , 01.06.2016 list of figures figure 1 typical application ................................ ................................ ................................ ............................... 8 figure 2 block diagram for 2edl23x06pj ................................ ................................ ................................ ......... 9 figure 3 pin configuration of 2edl family ................................ ................................ ................................ ....... 10 figure 4 input pin structure ................................ ................................ ................................ ............................... 11 figure 5 input filter timing diagram ................................ ................................ ................................ ................... 11 figure 6 en - /flt pin structures and interface to microcontroller (c) ................................ ............................ 12 figure 7 timing of short pulse suppression ................................ ................................ ................................ ..... 19 figure 8 timing of of internal deadtime ................................ ................................ ................................ ............ 19 figure 9 enable delay time definition ................................ ................................ ................................ ............... 19 figure 10 input to output propagation delay times and switching times definition ................................ ............. 20 figure 11 operating areas (igbt uvlo levels) ................................ ................................ ................................ . 20 figure 12 operating areas (mosfet uvlo levels) ................................ ................................ .......................... 20 figure 13 itrip - timing ................................ ................................ ................................ ................................ ...... 21 figure 14 output pulse width timing and matching delay timing diagram for positive logic ............................... 21 figure 15 package drawing ................................ ................................ ................................ ................................ 22 figure 16 pcb reference layout (accordin g to jedec 1s0p) left: reference layout right: detail of footprint .... 22
eicedriver? compact 2edl family final datasheet 6 , 01.06.2016 list of tables table 1 members of 2edl family ................................ ................................ ................................ ...................... 7 table 2 pin description ................................ ................................ ................................ ................................ ... 10 table 3 abs. maximum ratings ................................ ................................ ................................ ........................ 14 table 4 required operation conditions ................................ ................................ ................................ .......... 15 table 5 operating range ................................ ................................ ................................ ................................ . 15 table 6 static parameters ................................ ................................ ................................ ............................... 16 ta ble 7 dynamic parameters ................................ ................................ ................................ .......................... 18 table 8 data of reference layout ................................ ................................ ................................ ..................... 22
eicedriver? compact 2edl family final datasheet 7 , 01.06.2016 eicedriver? compact 600 v half bridge gate drive ic 1 overview main features ? thin - film - soi - technology ? maximum blocking voltage +600v ? individual control circuits for both outputs ? filtered d etection of under voltage supply ? all inputs clamped by diodes ? active shut down function ? asymmetric undervoltage lockout thresholds for high side and low side ? qualified according to jedec 1 (high temperature stress tests for 1000h) for target applications p roduct highlights ? insensitivity of the bridge output to negative transient voltages up to - 50v given by soi - technology ? ultra fast bootstrap diode ? overcurrent comparator ? enable function, fault indicator typical applications ? home appliances ? consumer electronics ? f ans, pumps ? general purpose drives product family table 1 members of 2 ed l family sales name special function output current target transistor typ. ls uvlo - t hresholds bootstrap diode package 2edl 23 i06p j deadtime, interlock, enable, fault, ocp 2.3 a igbt 12.5 v / 11. 6 v yes dso - 14 2edl 23n06pj deadtime, interlock, enable, fault, ocp 2.3 a mosfet 9 .1 v / 8.3 v yes dso - 14 1 j - std - 020 and jesd - 022 pg - dso - 14
eicedriver? compact 2edl family final datasheet 8 , 01.06.2016 description the 2edl family contains devices, which control power devices like mos - transistors or igbts with a maximum blocking voltage of +600v in half bridge configurations. based on the used soi - technology there is an excellent ruggedness on transient voltages. no parasitic thyristor structures are present in the device. hence, no parasitic latch up may occur at all temperature and voltage conditions. the two independent drivers outputs are controlled at the low - side using two different cmos resp. lsttl compatible signals, down up to 3.3v logic. the device includes an under - volta ge detection unit with hysteresis characteristic which are optimised either for igbt or mosfet . those parts, which are designed for igbt have asymmetric undervoltage lockout levels, which support strongly the integrated ultrafast bootstrap diode. additionally, the offline gate clamping function provides an inherent protection of the transistors for parasitic turn - on by floating gate conditions, when the ic is not supplied via vdd . figure 1 typical application l i n h o v s l o p g n d t o l o a d g n d h i n + d c - b u s g n d - d c - b u s 2 e d l 2 3 x 0 6 p j e n - / f l t t o o p a m p / c o m p a r a t o r v d d v b e n / c t r a p p w m _ h p w m _ l g n d + 5 v
eicedriver? compact 2edl family final datasheet 9 , 01.06.2016 2 blockdiagram figure 2 block d iagram for 2edl2 3 x06p j
eicedriver? compact 2edl family final datasheet 10 , 01.06.2016 3 pin c onfiguration , d escription , and functionality 3.1 pin configuration and description figure 3 pin configuration of 2edl family table 2 pin description symbol description vdd low side power supply gnd logic ground hin high side logic input lin low s ide logic input en - /flt enable input and fault indication output pgnd low side gate driver reference vb high side positive power supply ho high side gate driver output vs high side negative power supply lo low side gate driver output nc not connected 3.2 low side and high side control pins ( lin, hin ) 3.2.1 input voltage range all input pins have the capability to process input voltages up to the supply voltage of the ic. the inputs are therefore internally clamped to vdd and gnd by diodes . an internal pull - down resistor is high ohmic, so that it can keep the ic in a safe state in case of pcb crack. 3.2.2 switching levels the schmitt trigger input threshold is such to guarantee lsttl and cmos compatibility down to 3.3 v controller outputs. the i nput s chmitt trigger and noise filter provide beneficial noise rejection to short input pulses according to figure 4 and f igure 5 . please note, that the switching levels of the input structures remain constant even though they can accept amplitudes up to the ic supply level. v d d 1 1 4 h i n 2 1 3 3 1 2 4 1 1 l i n 5 1 0 6 9 7 8 g n d l o n c n c 1 8 2 7 3 6 4 5 2 e d l ( s o 8 ) 2 e d l ( 0 . 5 a , s o 1 4 ) 2 e d l ( 2 . 3 a , s o 1 4 ) n c v b h o v s n c v d d 1 1 4 h i n 2 1 3 3 1 2 4 1 1 l i n 5 1 0 6 9 7 8 g n d p g n d l o n c n c e n - / f l t n c v b h o v s n c n c n c v d d v b h i n h o v s l i n g n d l o
eicedriver? compact 2edl family final datasheet 11 , 01.06.2016 figure 4 input pin structure 3.2.3 input filter time figure 5 input filter timing diagram short pulses are suppressed by means of an input filter . the mosfet version (2edl23n06pj) ha s an input filter ti me of t filin = 100 ns typ. for high side and 150ns typ. for low side . the igbt version (2EDL23I06PJ) ha s filter time s of 1 9 0ns typ. 3.3 vdd , gnd and pgnd (low side supply) vdd is the low side supply and it provides power to both the input logic and the low side output power stage. the i nput logic is referenced to gnd ground as well as the under - voltage detection circuit. output power stage is referenced to pgnd ground. pgnd ground is floating respect to gnd ground with a n absolute maximum range of operation of +/ - 5.7 v. a back - to - back zener structure protects grounds from noise spikes. the under voltage lockout circuit enables the device to operate at power on when a typical supply voltage higher than v dd uv+ is present. please see section 3.6 undervoltage lockout for further information. a filter time of typ. 1. 5 s 1 helps to suppress noise from the uvlo circuit, so that neg ative going voltage spikes at the supply pins will avoid parasitic uvlo events. 3.4 vb and v s (high side supplies) vb to vs is the high side supply voltage. the high side circuit can float with respect to gnd following the external high side power device emitter/source voltage. due to the low power consumption, the floating driver stage can be sup plied by bootstrap topology connected to vdd . a filter time of typ. 1.3 s helps to suppress noise from the uvlo circuit, so that negative going voltage spikes at the supply pins will avoid parasitic uvlo events. the under - voltage circuit enables the devic e to operate at power on when a typical supply voltage higher than v dd uv+ is present. please see section 3.6 undervoltage lockout for further information. details on bootstrap supply section and transient immunity can be found in application note eicedriver? 2edl fa mily: technical description . 3.5 lo and ho (low and high side outputs) low side and high side power outputs are specifically designed for pulse operation such as gate drive f or igbt and mos fet devices. low side output is state triggered by the respective inpu ts, while high side output is edge triggered by the respective inputs . in particular, after an under voltage condition of the vbs supply, a new turn - on signal (edge) is necessary to activate the high side output . in contrast, the low side outputs switch to the state of their respective inputs after a n under voltage condition of the vdd supply . the output current specification i o+ and i o - is defined in a way, which considers the power transistors miller voltage.this helps to design the gate drive better in ter ms of the application needs. nevertheless, the devices are also characterised for the value of the pulse short circuit value i opk + and i opk C . v z = 5 . 2 5 v i n p u t n o i s e f i l t e r v i h ; v i l i l i n i h i n l i n x h i n x v c c 2 e d l - f a m i l y l i n h i n l i n l o h o l o h i g h l o w t f i l i n t f i l i n a ) b )
eicedriver? compact 2edl family final datasheet 12 , 01.06.2016 3.6 undervoltage lockout ( uvlo ) two different uvlo options are required for igbt and mosfet. the types 2edl23i06p j are designed to drive igbt. there are higher levels of undervoltage lockout for the low side uvlo than for the high side . this supports an improved start up of the ic, when bootstrapping is used. the thresholds for the low side are typically v dd uv+ = 12.5 v (positive going) and v dd uv C = 11.6 v (negative going). the thresholds for the high side are typically v bs uv+ = 11.6 v (positive going) and v bs uv C = 10.7 v (negative going). the types 2edl23n06p j are designed to drive power mosfet. a similar distinction for the high side and low side uvlo threshold as for igbt is not realised here. the ic shuts down all the gate drivers power outputs, when the supply voltage is below typ. v dd uv - = 8. 3 v (min. / max . = 7.5 v / 9 v) . th e turn - on threshold is typ. v dd uv + = 9 .1 v (min. / max. = 8.3 v / 9.9 v) 3.7 bootstrap diode an ultra fast bootstrap diode is monolithically integrated for establishing the high side supply. the differential resistor of the diode helps to avoid extremely high inrush currents when charging the bootstrap capacitor initially. 3.8 deadtime and interlock function the ic provides a hardware fixed deadtime. the deadtime is different for the mosfet type (2edl23n06p j ) and for the igbt type (2edl23i06p j ). the deadtimes are particularly typ. 38 0 ns for igbt a nd typ. 75 ns for mosfet. an additional interlock function prevents the two outputs from being activated simultaneously. 3.9 en - /flt (fault indication and e nable function ) the types 2edl23x06p j provide a pin, which can either be used to shut down the ic or to read out a failure status of the ic. the signal applied to pin en controls directly the output stages. all outputs are set to low, if en is at low logic level. an integrated pull down resis tor shuts down the ic in case of a floating input. the internal structure of the pin is given in figure 6 . t he switchin g levels of the schmitt - trigger are here v en ,th+ = 2.1 v and v en,th - = 0.9 v. the typical propagation delay time is t en = 5 5 0 ns. the input is clamped by diode s to vdd and gnd . the input voltage range is the same as the input control pins with a max. of 20 v. the /f au lt function is an active low open - drain output indicating the status of the gate driver (see figure 6 ). the pin is active (i.e. forces low voltage level) when one of the follo wing conditions occur: ? under - voltage condition of vdd supply: in this case the fault condition is released as soon as the supply voltage condition returns in the normal operation range (please refer to vdd pin description for more details ). the fault signa l is activate as long as uvlo is given during power up. ? overcurrent detection ( itrip ): the fault condition is latched until the overc urrent tri gger condition is finished and additional typ. 230 s are elapsed. the interface to the microcontroller can be realised by using an open collector / drain configured output pin for enabling the driver ic and a gpio pin for monitoring the /fault. the external pull - up resistor will pull - up the voltage to +5v, when the ic is set for opera tion. figure 6 en - /flt pin structures and interface to microcontroller (c) g n d 2 e d l 2 3 x e n - / f l t l a t c h 2 3 0 s t o l o g i c r p u c f l t g p i o 7 3 k w + 5 v r o n , f l t 3 5 w f r o m i t r i p - f i l t e r c o r f r o m u v l o e n
eicedriver? compact 2edl family final datasheet 13 , 01.06.2016 3.10 power ground / over current protection a power ground (pgnd) connects directly the emitter or source of the low side transistor with the gate drive ic. no other components, such as shunts, etc., are between this connection and the emitter or source. this enables the routing of smallest gate cir cuit loops an d therefore smallest gate inductances. a potential shunt resistor is between the power ground (pgnd) connection and the gound connection (gnd), which leads to a voltage drop between these two pins. the voltage drop between pgnd and gnd can b e seen sensed by means of a comparator with a threshold of v th, itrip = 0. 4 6 v . if the voltage drop is larger than v th, itrip , then t he output of the comparator is triggered and the /flt output is activated. simultaneously, the ic shuts down both gate outputs for the period of the fault indication, which is 2 3 0 s . several influences, such as reverse recovery currents, parasitic inductances and other noise sources, make the need of a signal filter necessary. the filter ha s a time constant of typically 1 . 8 s to ensure good noise quality. __________________________ _______ 1 not subject of production test, verified by characterisation
eicedriver? compact 2edl family final datasheet 14 , 01.06.2016 4 electrical parameters 4.1 absolute maximum ratings all voltages are absolute voltages referenced to v gnd - potential unless otherwise specified. ( t a =25c) table 3 abs. maximum ratings parameter symbol min. max. unit high side offset voltage (note 1 ) v s v dd - v bs - 6 600 v high side offset voltage ( t p <500ns , note 1 ) v dd - v bs C C v b v dd C t p <500ns , note 1 ) v dd C C v b vs. v s ) (internally clamped) v bs - 1 20 high side output voltage ( v ho vs. v s ) v ho - 0.5 v b + 0.5 low side supply voltage (internally clamped) v dd - 1 20 low side supply voltage ( v dd vs. v pgnd ) v dd pgnd - 0.5 25 gate driver ground v pgnd - 5.7 5.7 low side output voltage ( v lo vs. v pgnd ) v lo - 0.5 v dd pgnd + 0.5 input voltage lin,hin,en v in - 0.5 v dd + 0.5 fault output voltage v flt - 0.5 v dd + 0.5 power dissi pation (to package) ( note 2 ) p d C 0.9 w thermal resistanc e (junction to ambient, see section 6 ) r th(j - a) C 134 k/w junction temperature (note 3) t j C t s - 40 150 offset voltage slew rate (note 4) d v s /dt C note :the minimum value for esd immunity is 1.0kv (human body model). esd immunity inside pins connected to the low side ( vdd , hin, lin, fault, en, gnd, pgnd , lo) and pins connected inside each high side itself (vb, ho, vs) is guaranteed up to 1.5kv (human body mod el) re s pectively . note 1 : in case v dd > v b there is an additional power dissipation in the internal bootstrap diode between pins vdd and vb in case of activated bootstrap diode . insensitivity of bridge output to negative transient voltage up to C 50v is n ot subject to production test C verified by design / characterization. note 2: consistent power dissipation of all outputs . all parameters are inside operating range. note 3 : qualification stress tests cover a max. junction temperature of 150c for 1000 h . note 4: not subject of production test, verified by characterisation.
eicedriver? compact 2edl family final datasheet 15 , 01.06.2016 4.2 required operation conditions all voltages are absolute voltages referenced to v gnd - potential unless otherwise specified. ( t a = 25c) table 4 required operation conditions parameter symbol min. max. unit high side offset voltage (note 1 ) v b 7 620 v low side supply voltage ( v dd vs. v pgnd ) v dd pgnd 10 25 4.3 operating range all voltages are absolute voltages referenced to v gnd - potential unless otherwise specified. ( t a = 25c) table 5 operating range parameter symbol min. max. unit high side floating supply offset voltage v s v dd - v bs - 1 500 v high side floating supply offset voltage ( v b vs. v dd , statically) v b dd - 1.0 500 high side floating supply voltage ( v b vs. v s , note 1) igbt - types v bs 13 17.5 mosfet - types 10 17.5 high side output voltage ( v ho vs. v s ) v ho 10 v bs low side output voltage ( v lo vs. v pgnd ) v lo 0 v dd low side supply voltage igbt - types v dd 13 17.5 mosfet - types 10 17.5 low side ground voltage v pgnd - 2.5 2.5 logic input voltages lin,hin,en ( note 2) v in 0 17. 5 fault output voltage v flt 0 v dd pulse width for on or off (note 3) igbt - types t in 0. 8 C C t a - 40 1 05 c thermal resistanc e dso8 (junction to ambient, see section 6 ) dso14 ? th(j - top) C C note 1 : logic operational for v b ( v b vs. v gnd ) > 7. 0v note 2 : all input pins (hin, lin) and en pin are internally clamped (see abs. maximum ratings) note 3 : t he input pulse may not be transmitted properly i n case of input pulse width at lin and hin below 0.8 s (igbt types) or 0.3 s (mosfet) respectively
eicedriver? compact 2edl family final datasheet 16 , 01.06.2016 4.4 static l ogic f unction t able vdd vbs enable fault pgnd lo ho < v dd uv C x x 0 x 0 0 15v < v bsuv C 3.3 v high imp . < v th,itrip lin 0 15v 15v 3.3 v 0 > v th,itrip 0 0 15v 15v 0 v high imp. x 0 0 15v 15v 3.3 v high imp. < v th,itrip lin hin a ll voltages with reference to gnd 4.5 s tatic p arameters v dd = v bs = 15v unless otherwise specified. ( t a = 25c) and v gnd = v pgnd unless otherwise specified table 6 static parameters parameter symbol values unit test condition min. typ. max. high level input voltage v ih 1.7 2.1 2.4 v low level input voltage v il 0.7 0.9 1.1 en positive going threshold v en,th+ 1.7 2.1 2.4 en negative going threshold v en,th C 0.7 0.9 1.1 high level output voltage lo ho v oh C C v dd - 0. 32 v b - 0. 32 v dd - 0 . 7 v b - 0 . 7 i o = - 100 ma high level output voltage lo ho v ol C C v pgnd + 0. 18 v s + 0. 18 v pgnd - 0 .4 v s + 0 .4 i o = 100 m a v dd supply undervoltage positive going threshold igbt - types v dd uv+ 11.8 12.5 13.2 mosfet types 8.3 9 .1 9. 9 v bs supply undervoltage positive going threshold igbt - types v bsuv + 10.9 11.6 12.4 mosfet types 8.3 9 .1 9. 9 v dd supply undervoltage negative going threshold igbt - types v dd uv C 10.9 11.6 12.4 mosfet types 7.5 8. 3 9 v bs supply undervoltage nega tive going threshold igbt - types v bsuv C v dd and v bs supply uvlo hysteresis igbt - types v dd uvh v bsuvh 0.5 0.9 C C v th,itrip 0. 4 0.4 6 0.5 3 v itrip = v pgnd - v gnd itrip comparator hysteresis v th,itrip hys 0.045 0.07 C i lvs+ C v s = 600v high side leakage current betw. vs and gnd i lvs+ 1 C C t j = 125 c, v s = 600 v 1 not subject of production test, verified by characterisation
eicedriver? compact 2edl family final datasheet 17 , 01.06.2016 table 6 static parameters parameter symbol values unit test condition min. typ. max. quiescent current v bs supply (vb only) i qbs1 C v bs supply (vb only) i qbs2 C i q dd 1 C v lin = float quiescent current vdd supply ( vdd only) i q dd 2 C v lin = 3.3 v, v hin =0 quiescent current vdd supply ( vdd only) i q dd 3 C v lin =0 , v hin =3.3 v input bias current i lin+ 15 35 6 0 a v lin = 3.3 v input bias current i lin C C C v lin = 0 input bias current i h in+ 15 35 6 0 v h in = 3.3 v input bias current i h in C C C v h in = 0 input bias current (en=high) i en+ C v enable = 3.3 v mean output current for load capacity charging in range from 4.5 ( 30% ) to 7.5v ( 50% ) i o+ 1.3 1.8 C l = 61 nf peak output current turn on (single pulse) i opk+ 1 C C l = 0 w t p <10 s mean output current for load capacity discharging in range from 7.5v (50%) to 4.5v (30%) i o C 1.65 2. 5 C l = 61 nf peak output current turn off (single pulse) i opk C 1 C C r l = 0 w t p <10 s bootstrap diode forward voltag e between vdd and vb v f,bsd C i f = 0. 3 m a bootstrap diode forward current between vdd and vb i f,bsd 45 82 120 ma v dd C v b = 4 v bootstrap diode resistance r bsd 15 27 40 w v f 1 = 4 v, v f 2 = 5 v en - /flt low on resistance of the pull down transistor r on,flt C v en - /f lt = 0.5 v 1 not subject of production test, verified by characterisation
eicedriver? compact 2edl family final datasheet 18 , 01.06.2016 4.6 dynamic parameters v dd = v bs = 15 v , v s = v gnd = v pgnd , c l = 180 pf unless otherwise specified. ( t a =25c) table 7 dynamic parameters parameter symbol values unit test condition min. typ. max. turn - on propagation delay igbt types t on 28 0 4 2 0 6 1 0 ns v lin/hin = 0 or 3.3 v mosfet types 2 1 0 3 1 0 4 6 0 turn - off propagation delay igbt types t off 2 6 0 40 0 5 9 0 mosfet types 2 0 0 30 0 4 4 0 turn - on rise time t r C v lin/hin = 0 or 3.3 v c l = 4.9 nf turn - off fall time t f C t en C v en =0 .5 v , v lo / v ho = 2 0% input filter time at lin/hin for turn on and off igbt types t filin 120 19 0 320 v lin/hin = 0 & 3.3 v mosfet types hin lin 50 100 1 0 0 150 1 7 0 250 input filter time en t filen 2 00 4 00 C t filitrip 1. 0 1 . 8 2.7 s v pgnd = 1 v, /flt=0 shut down propoagation delay pgnd to any output t itrip 1. 1 2.2 3.0 v pgnd = 1 v v lo / v ho = 3v propagation delay itrip to fault t flt 1. 0 2.1 2. 9 v pgnd = 1 v, /flt=0 .5 v fault - clear time t fltclr 70 23 0 C v pgnd = 0.1 v, /flt=2.1 v dead time igbt types dt 260 38 0 540 ns v lin/hin = 0 & 3.3 v mosfet types 30 75 140 dead time matching abs(dt_lh C mdt C C mt on C mt off C in - pw out igbt types pm C in > 1 s mosfet types C
eicedriver? compact 2edl family final datasheet 19 , 01.06.2016 5 timing diagrams figure 7 timing of short pulse suppression figure 8 timing of of internal deadtime figure 9 enable delay time definition l i n 1 , 2 , 3 h i n 1 , 2 , 3 h o 1 , 2 , 3 l o 1 , 2 , 3 1 2 v 3 v 3 v 1 2 v 1 . 6 5 v 1 . 6 5 v d t d t h i n / l i n h i n / l i n h o / l o h o / l o l o w t i n < t f i l i n t i n t i n > t f i l i n t f i l i n t i n h i n / l i n h i n / l i n h o / l o h o / l o h i g h t f i l i n t i n < t f i l i n t i n t i n > t f i l i n t i n l o 1 , 2 , 3 t e n 3 v h o 1 , 2 , 3 e n
eicedriver? compact 2edl family final datasheet 20 , 01.06.2016 figure 10 input to output propagation delay times and switching times definition figure 11 operating areas ( igbt uvlo levels ) figure 12 operating a reas ( mosfet uvlo levels ) l i n 1 , 2 , 3 h i n 1 , 2 , 3 h o 1 , 2 , 3 l o 1 , 2 , 3 1 . 6 5 v 1 . 6 5 v 1 2 v 3 v 3 v 1 2 v p w o u t t o n t o f f t r t f p w i n
eicedriver? compact 2edl family final datasheet 21 , 01.06.2016 figure 13 itrip - timing figure 14 output pulse width timing and matching delay timing diagram for positive logic h i n / l i n h o / l o p w i n p w o u t m t o n p m = p w i n - p w o u t h i n / l i n p w i n h o / l o m t o f f p m = p w i n - p w o u t p w o u t p g n d 2 . 1 v f a u l t a n y o u t p u t 0 . 1 v 1 v t f l t c l r 0 . 5 v t f l t t i t r i p 3 v
eicedriver? compact 2edl family final datasheet 22 , 01.06.2016 6 package 6.1 pg - dso - 14 max. reflow solder temperature: 265c acc. jedec max. wave solder temperature: 245c acc. jedec figure 15 package drawing figure 16 pcb reference layout (according to jedec 1s0p) left: reference layout right: detail of footprint the thermal coefficient is used to calculate the junction temperature, when the ic surface temperature is measured. the junction temperature is ? j = th(j - top) ? ? ? + ? top table 8 data of reference layout dimensions material metal (copper) 76.2 ? ? ? therm = 0.3 w/mk) 70m ( ? therm = 388 w/mk)
w w w . i n f i n e o n . c o m published by infineon technologies ag
|
